Side-Channel Risks Across Advanced Chiplet Packages (UGA, CNRS) - Semiconductor Engineering

Researchers from Grenoble INP – UGA and CNRS’s TIMA have unveiled a significant security vulnerability in advanced chiplet-based systems, demonstrating that side-channel attacks can be executed across... Read original →

The chiplet security gap has shifted from theoretical concern to tangible threat. Researchers demonstrated that communication modules—originally for RFID or contactless coupling—can be weaponized as internal eavesdropping channels across 2.5D/3D stacks, exposing the illusion of physical isolation. Technically, EDA flows and interposer designs must now embed dynamic EM leakage models. Compliance-wise, standards like ISO/IEC 17826 and NIST SP 800-193 will soon mandate chiplet-level side-channel audits, raising certification costs for AI/HPC chips. Strategically, Intel’s EMIB and TSMC’s (Taiwan, China) SoIC will need to expose hardened physical-layer defenses, while AMD and NVIDIA may push a 'Trusted Chiplet' consortium. Within 18 months, active shielding and noise obfuscation will become non-negotiable IP features—security is no longer just logical, but a prerequisite for advanced packaging itself.