The Changing ASICs Landscape: the Shift Toward Chip Disaggregation

The rapid rise of AI is fundamentally reshaping ASIC design, pushing the industry toward chip disaggregation. Traditional monolithic approaches are being challenged by increasingly diverse, compute-in... Read original →

The AI-driven shift from monolithic SoCs to multi-die ASICs isn't just an advanced packaging trend—it's a full-stack disruption. Upstream, EDA flows must evolve to handle cross-die RTL verification and thermal-electrical co-analysis, pushing Siemens EDA to deepen physical-aware synthesis. Downstream, GUC and Wiwynn face yield risks from micro-bumps and wafer-to-wafer bonding, demanding new test methodologies. Geopolitically, access to EUV and hybrid bonding tools is as constrained as leading-edge nodes; TSMC’s CoWoS capacity has become a national-security-grade bottleneck. NVIDIA’s Grace-Hopper architecture sets a system-level benchmark, forcing AMD and Intel to counter with open chiplet ecosystems. Within 18 months, disaggregation will spread beyond AI inference into 5G RAN and autonomous driving—but without UCIe-compliant interconnects, many players will drown in custom, non-reusable die designs.