TSMC Accelerates CoPoS Packaging to Replace CoWoS, as Glass Core Substrates Cut Costs 30% and Boost Wafer Utilization Past 90% - Wccftech

Taiwan Semiconductor Manufacturing Company (TSMC) is aggressively advancing CoPoS (Chip-on-Panel-on-Substrate) packaging to replace the existing CoWoS (Chip-on-Wafer-on-Substrate) technology in respon... Read original →

TSMC’s aggressive pivot to CoPoS isn’t just an evolution—it’s a structural break from CoWoS, driven by glass core substrates that slash costs by 30% and push panel utilization beyond 90%. This shift forces upstream players like Ibiden to retool away from ABF, while Innolux gains strategic leverage. Intel’s parallel glass roadmap at Rio Rancho remains hamstrung by its delayed 1.4nm node, leaving it vulnerable to TSMC’s 2027 pilot timeline. Geopolitically, U.S. incentives accelerate Arizona’s role but inflate compliance overhead. Within 12–24 months, AMD and Amkor must realign packaging strategies, and glass yield rates will dictate AI chip economics. If TSMC hits its 2027 milestones, CoWoS becomes obsolete by 2030—ushering in the era of panel-level advanced packaging.