TSMC highlights CoWoS strength over panel packaging for largest AI chips - Let's Data Science

At TSMC's European Technology Symposium on June 16, 2026, senior vice president Kevin Zhang emphasized the advantages of CoWoS (Chip on Wafer on Substrate) over panel-level packaging technologies like... Read original →

TSMC’s explicit dismissal of panel-level packaging for large AI chips at its 2026 European symposium is a strategic signal, not just a technical preference. Technically, CoWoS’s superior interconnect density forces upstream EDA, interposer, and substrate suppliers to co-evolve—panel approaches simply can’t meet the geometric precision needed for 58-die integration. On compliance, U.S. CHIPS Act mandates for domestic advanced packaging raise adoption risks for alternative routes, reinforcing CoWoS’s policy-aligned dominance. Competitively, Samsung and Intel may push Foveros or I-Cube variants, but without equivalent interposer capacity, scale remains elusive. Over the next 12–24 months, AI chip leadership will pivot from transistor count to package-level bandwidth; only players integrating silicon photonics with wafer-scale packaging like TSMC will capture the high-end market, relegating panel-level methods to mid-tier applications.