Samsung Foundry’s plan to launch its 'Physical AI' chiplet platform by early 2027 might sound like just another foundry roadmap update. But if you’re only reading the headlines—'5nm', 'NPU', 'robotics and automotive AI'—you’re missing the real story. This isn’t merely a product announcement; it’s a tectonic shift from the era of bespoke silicon empires toward a democratized, modular future.
For two decades, chip design was the preserve of giants. NVIDIA built moats with CUDA, Apple and Qualcomm locked in users with vertically integrated SoCs, and TSMC dictated terms through wafer scarcity. Now, Samsung’s collaboration with Cadence Design Systems on a pre-integrated, reusable chiplet platform signals something far more subversive: the unbundling of the monolithic SoC.
Cadence isn’t just supplying EDA tools here—it’s becoming the architectural glue of the chiplet age. By offering pre-validated PHYs, memory controllers, and interconnect IP, Cadence transforms Samsung’s SF5A 5nm node from a mere manufacturing process into a deliverable system-level solution. Customers no longer need to start from scratch; they can assemble CPU, NPU, and I/O blocks like Lego bricks. Efficiency gains aside, this is a fundamental redefinition of the chip design workflow.
And the true architects of this unbundling? Arm and Arteris.
Arm provides standardized compute blocks—Cortex CPUs, Ethos NPUs, and increasingly, coherent interconnect fabrics like CMN. But Arm’s ambition stretches beyond licensing cores. It’s positioning itself as a system definer for the fragmented edge-AI market, where few can afford full-custom silicon. The strategy is clear: lower barriers to entry, expand the ecosystem, and let scale do the rest.
Yet Arm doesn’t own the interconnect narrative alone. Enter Arteris—a quiet but pivotal French firm specializing in Network-on-Chip (NoC) and cache-coherency protocols. In chiplet architectures, communication between dies dictates performance ceilings. Arteris’ FlexNoC and CacheStash technologies enable low-latency, power-efficient data flow across heterogeneous chiplets. Crucially, they’re ISA-agnostic: whether you’re using Arm, RISC-V, or proprietary cores, integration remains seamless.
That’s the crux: in a modular world, control over connectivity standards equals control over the stack.
Together with physical IP vendors like M31 Technology, Silicon Creations, and eMemory from Taiwan, China and Korea, Cadence, Arm, and Arteris are weaving a new infrastructure layer beneath chip design—one that bypasses traditional IDM verticality and erodes NVIDIA’s full-stack advantage. Tesla, Qualcomm, even Huawei can now rapidly prototype domain-specific AI accelerators without waiting three years for tape-out.
I believe the next three years won’t be won on transistor density, but on integration velocity and ecosystem compatibility. If Samsung’s Physical AI platform gains traction, it will force TSMC to accelerate commercialization of its TSMC-SoIC and 3DFabric offerings, while Intel’s EMIB and Foveros face pressure from open chiplet ecosystems.
But here’s the paradox: when anyone can assemble an AI chip in weeks, where does differentiation come from?
Algorithms? Software stacks? System-level co-optimization?
Perhaps the answer lies with firms like proteanTecs and Trilinear Technologies. The former embeds telemetry agents to monitor chip health in real time; the latter specializes in high-speed SerDes and signal integrity. They represent the new moat of the chiplet era—not how many advanced blocks you use, but how reliably and efficiently they cooperate under real-world conditions.
History echoes. In the 1990s, the PC industry shifted from IBM clones to the Wintel duopoly not through monopoly, but through interface standardization—PCI, USB, AGP. Today’s chiplet revolution may be replaying that script, with UCIe (Universal Chiplet Interconnect Express) as the new USB, and Arm or Arteris as the de facto architects of interoperability.
So stop obsessing over 3nm or 2nm. The real battlefield has moved to the few micrometers between chiplets—the silent corridors where standards, efficiency, and control are being contested.
When chips become Lego, who gets to write the instruction manual?