Semiconductor News & Analysis Feed

On June 25, IBM unveiled what it calls the world's first sub-1nm chip technology: a 0.7nm — or 7 angstrom — transistor architecture built on an entirely new 3D platform called Nanostack. The announcement, timed to the VLSI 2026 symposium, marks the first time logic technology has extended below the 1nm node and, IBM says, opens a roadmap of at least a decade of further semiconductor scaling.

Researchers and chipmakers presented new logic, memory, and device architectures at the 2026 IEEE/JSAP VLSI Technology and Circuits Symposium in Honolulu, with several results pointing toward pilot production and mass manufacturing.

ASML, TSMC, and imec have demonstrated a major advance in the effort to bring two-dimensional (2D) semiconductor materials from research laboratories into high-volume semiconductor manufacturing. At the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, the partners unveiled a 300mm wafer integration flow that produced both n-type and p-type 2D-material transistors at a 50nm contacted poly