Baya Systems partners with Openchip for RISC-V systems - SDxCentral

Baya Systems and Openchip have formed a strategic partnership to advance the development of intelligent computing systems based on the RISC-V architecture. Central to this collaboration is Baya's Weav... Read original →

The Baya–Openchip alliance represents a surgical strike by the RISC-V ecosystem against x86/ARM dominance in AI and HPC. By tightly integrating WeaveIP’s NoC with UCIe, they shift chiplet design from physical assembly to logical co-optimization—directly threatening Synopsys’ and Cadence’s interconnect IP pricing power. This forces EDA vendors to embed data-movement modeling or risk obsolescence. Geopolitically, both avoid U.S. export controls, yet Intel Capital’s influence could trigger EU scrutiny over non-neutral capital shaping open architectures. Competitively, SiFive may fast-track TSMC co-designs, while Arm quietly readies a chiplet-enabled Neoverse V3 for data centers. Within 18 months, if RISC-V SoCs surpass 3 TOPS/W efficiency, they’ll capture over 30% of the edge AI chip market—eroding closed ISA moats permanently.