Europe's chip plan failed to hit its target, now they're switching to chiplets and packaging instead - Cybernews

Europe's chip industry plan encountered setbacks, failing to achieve its targets and forcing the region to reassess its technology development path. This shift reflects the profound changes in the glo... Read original →

Europe’s pivot from advanced nodes to chiplets and packaging isn’t retreat—it’s a pragmatic acknowledgment that Moore’s Law is hitting physical limits. Abandoning direct competition with TSMC (Taiwan, China) in 3nm fabrication shifts focus to heterogeneous integration, forcing EDA vendors and materials suppliers to adapt to silicon interposers and hybrid bonding standards. While this avoids massive fab CAPEX, it heightens supply chain sovereignty risks under the EU and U.S. Chips Acts’ localization mandates. TSMC already dominates AI packaging via CoWoS; without a domestic advanced packaging ecosystem, Europe risks marginalization in system-level innovation. Over the next 12–24 months, chiplet standardization (e.g., UCIe) will become a new geopolitical battleground. Europe may leverage automotive and industrial applications to build differentiated IP ecosystems—but without manufacturing anchors, its 'system-level competitiveness' remains hostage to Asian capacity.