IBM goes sub-1nm, develops 0.7nm-class technology — offering up to 50% higher performance and 70% higher energy efficiency compared to IBM's 2nm-class node - Tom's Hardware

IBM has announced the development of the industry's first sub-1nm fabrication process, a 0.7nm-class technology based on nanostack transistors. Compared to its 2nm node, this new process delivers up t... Read original →

IBM’s 0.7nm breakthrough sidesteps High-NA EUV dependency by leveraging nanostack CFETs, triggering cascading demands in EDA, thermal solutions, and 3D SRAM design. Geopolitically, reliance on Low-NA tools mitigates export control exposure, yet ultra-precise wafer bonding raises manufacturing barriers—likely confining production to advanced hubs like Taiwan, China and limiting broader foundry adoption. TSMC and Samsung will likely accelerate CFET prototyping but favor High-NA EUV to preserve roadmap credibility, avoiding IBM’s complex dual-wafer approach. Within 18 months, while commercialization remains distant, this node will reset AI accelerator efficiency benchmarks, compelling NVIDIA and AMD to rethink chiplet interconnect strategies. The real race isn’t transistor scaling—it’s system-level power density.