Intel EMIB-T Breaks Past Existing AI & HPC Scaling Limits, Enabling Ultra-Large Die Complexes With Over 10x Reticle Dies & 12 Gb/s+ HBM4e DRAM - Wccftech

At the 2026 IEEE Electronic Components and Technology Conference (ECTC), Intel showcased its next-generation advanced packaging technology, EMIB-T, which marks a significant breakthrough in AI and Hig... Read original →

Intel’s EMIB-T isn’t just an advanced packaging leap—it redefines AI chip architecture. By fusing TSVs with silicon interposers, it bypasses reticle limits, enabling ultra-large heterogeneous integration and pressuring HBM4e suppliers like Micron and Samsung to accelerate 3D stacking yields. Against TSMC’s CoWoS, EMIB-T offers lower warpage risk and cost at 240mm² scale, potentially luring NVIDIA and Google away from CoWoS dominance in AI training chips. Geopolitically, reduced reliance on multi-patterning EUV eases U.S. export control bottlenecks, though supply chain vulnerabilities persist in advanced interposer materials from Taiwan, China. Within 18 months, the chiplet standards war will intensify: Intel will leverage EMIB-T to solidify UCIe adoption, likely forcing TSMC to open more CoWoS IP interfaces to retain ecosystem loyalty.