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Huawei's LogicFolding Revolution: Breaking Through Chip Design Barriers Huawei's innovative chip design principle, focusing on signal speed rather than shrinking semiconductors, introduces a new path for China amidst U.S. sanctions. Their approach, known as the Tau Scaling Law, seeks to enhance chip efficiency via tightly connected structures, although its true impact remains debated within the in

Tech Industry Manufacturing Semiconductors Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture — 3D design delivers increased performance and better thermal management News By Luke James published 20 minutes ago China now has a prototype tool designed for vertical circuit stacking. (Image credit: Getty Images) Share this article 0 Join the conversatio

The announcement came two days after Huawei presented LogicFolding and its accompanying Tau Scaling Law at ISCAS 2026.

Peking University researchers have unveiled a prototype electronic design automation (EDA) tool built for "true-3D" chip design, offering a potential missing link for Huawei's LogicFolding architecture and its broader Tau (τ) Scaling Law roadmap. Some subscribers prefer to save their log-in information so they do not have to enter their User ID and Password each time they visit the

Peking University researchers have unveiled a prototype electronic design automation (EDA) tool built for "true-3D" chip design, offering a potential missing link for Huawei's LogicFolding architecture and its broader Tau (τ) Scaling Law roadmap. Some subscribers prefer to save their log-in information so they do not have to enter their User ID and Password each time they visit the

Peking University researchers have unveiled a prototype electronic design automation (EDA) tool built for "true-3D" chip design, offering a potential missing link for Huawei's LogicFolding architecture and its broader Tau (τ) Scaling Law roadmap.

EMERGING TECHNOLOGIES Huawei is unveiling a new 3D chip design it says can close the gap with global leaders The Chinese tech giant says its new stacked-chip architecture can deliver transistor density equivalent to 1.4nm processes by 2031, without access to advanced lithography tools By Cris Tolomia Share to X Share to Facebook Share to Reddit Share to Email Share to Link Published 16 minutes ago

Artificial intelligence/Huawei Announces LogicFolding: 3D Density Without EUV Machines, Targeting 1.4 nm by 2031 Table of contents A Temporal Scaling Law to Succeed Moore LogicFolding: 3D Against EUV, and Its Shades A 3D Architecture That Isn't Uniquely Huawei's He Tingbo, the Tutelary Figure of HiSilicon On May 25, 2026, He Tingbo, president of Huawei's semiconductor department and board member

Flagship Huawei Mate 90 series will be the first commercial processors to feature the LogicFolding architecture

Tech Industry Manufacturing Semiconductors Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law News By Etiido Uko published 11 hours ago Flagship Huawei Mate 90 series will be the first commercial processo